Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is trimmed and ground to have one or more flats or notches for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers. While reference will be made herein to semiconductor wafers constructed from silicon, other materials may be used to prepare semiconductor wafers, such as silicon carbide, sapphire, and aluminum nitride.
Semiconductor wafers (e.g., silicon wafers) may be utilized in the preparation of composite layer structures. A composite layer structure (e.g., a semiconductor-on-insulator, and more specifically, a silicon-on-insulator (SOI) structure) generally comprises a handle wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Generally, the device layer is between 0.01 and 20 micrometers thick, such as between 0.05 and 20 micrometers thick. In general, composite layer structures, such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz, are produced by placing two wafers in intimate contact, followed by a thermal treatment to strengthen the bond.
After thermal anneal, the bonded structure undergoes further processing to remove a substantial portion of the donor wafer to achieve layer transfer. For example, wafer thinning techniques, e.g., etching or grinding, may be used, often referred to as back etch SOI (i.e., BESOI), wherein a silicon wafer is bound to the handle wafer and then slowly etched away until only a thin layer of silicon on the handle wafer remains. See, e.g., U.S. Pat. No. 5,189,500, the disclosure of which is incorporated herein by reference as if set forth in its entirety. This method is time-consuming and costly, wastes one of the substrates and generally does not have suitable thickness uniformity for layers thinner than a few microns.
Another common method of achieving layer transfer utilizes a hydrogen implant followed by thermally induced layer splitting. Particles (e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a specified depth beneath the front surface of the donor wafer. The implanted particles form a cleave plane in the donor wafer at the specified depth at which they were implanted. The surface of the donor wafer is cleaned to remove organic compounds deposited on the wafer during the implantation process.
The front surface of the donor wafer is then bonded to a handle wafer to form a bonded wafer through a hydrophilic bonding process. Prior to bonding, the donor wafer and/or handle wafer are activated by exposing the surfaces of the wafers to plasma containing, for example, oxygen or nitrogen. Exposure to the plasma modifies the structure of the surfaces in a process often referred to as surface activation, which activation process renders the surfaces of one or both of the donor water and handle wafer hydrophilic. The wafers are then pressed together, and a bond is formed there between. This bond is relatively weak, and must be strengthened before further processing can occur.
In some processes, the hydrophilic bond between the donor wafer and handle wafer (i.e., a bonded wafer) is strengthened by heating or annealing the bonded wafer pair. In some processes, wafer bonding may occur at low temperatures, such as between approximately 300° C. and 500° C. In some processes, wafer bonding may occur at high temperatures, such as between approximately 800° C. and 1100° C. The elevated temperatures cause the formation of covalent bonds between the adjoining surfaces of the donor wafer and the handle wafer, thus solidifying the bond between the donor wafer and the handle wafer. Concurrently with the heating or annealing of the bonded wafer, the particles earlier implanted in the donor wafer weaken the cleave plane.
A portion of the donor wafer is then separated (i.e., cleaved) along the cleave plane from the bonded wafer to form the SOI wafer. Cleaving may be carried out by placing the bonded wafer in a fixture in which mechanical force is applied perpendicular to the opposing sides of the bonded wafer in order to pull a portion of the donor wafer apart from the bonded wafer. According to some methods, suction cups are utilized to apply the mechanical force. The separation of the portion of the donor wafer is initiated by applying a mechanical wedge at the edge of the bonded wafer at the cleave plane in order to initiate propagation of a crack along the cleave plane. The mechanical force applied by the suction cups then pulls the portion of the donor wafer from the bonded wafer, thus forming an SOI wafer.
According to other methods, the bonded pair may instead be subjected to an elevated temperature over a period of time to separate the portion of the donor wafer from the bonded wafer. Exposure to the elevated temperature causes initiation and propagation of a crack along the cleave plane, thus separating a portion of the donor wafer. This method allows for better uniformity of the transferred layer and allows recycle of the donor wafer, but typically requires heating the implanted and bonded pair to temperatures approaching 500° C.
Crystal growth of bulk Group IIIA-nitrides, particularly GaN, is challenging and has not been successful in volume production. Conventionally, Group IIIA-nitrides, such as GaN, are produced by heteroepitaxial deposition on wafer substrates made of sapphire, silicon carbide, and silicon. Deposition of Group IIIA-nitrides on semiconductor wafers is challenging due to mismatch of the coefficient of thermal expansion (CTE) between GaN and the substrate, which leads to large bow of the wafer substrate and cracks in the deposited Group IIIA-nitride layer.
Conventionally, there have been several engineering approaches to address the residual stress in heteroepitaxially deposited Group IIIA-nitride, e.g., GaN, layers on semiconductor substrates. In one solution, Group IIIA-nitride layers are deposited on thick semiconductor substrates. For example, silicon substrates have been used having a thickness of at least about 1.0 millimeter, such as 1.5 millimeters have been used to reduce the wafer bow caused by the heteroepitaxially deposited GaN layer. This approach does not change the stress, but does mitigate stress induced substrate deformation by increasing the stiffness of the substrate. Although the wafer bow is reduced, the residual stress does not change and cracks in the GaN layer may still be present. Cracks are a killer defect for the growth of thick GaN layers (>5 um) as used in high-voltage power devices (>800V). Layer cracking and wafer bow become more severe when scaling the substrate diameter up to 200 mm or beyond.
In another technique for reducing defectivity in the deposited Group IIIA-nitride layer (e.g., GaN), a buffer layer having a thickness between about 2 micrometers and about 5 micrometers may be deposited on the wafer substrate prior to formation of the Group IIIA-nitride layer (e.g., GaN). The buffer layer may comprise aluminum nitride, aluminum gallium nitride, or a multilayer comprising aluminum nitride and aluminum gallium nitride. The residual stress in the AlN/AlGaN buffers tends to deform the substrate and thus creates temperature non-uniformity across the substrate, which results in non-uniformity in either layer thickness or composition. See Dadgar, Journal of Crystal Growth, 272 (2004) 72-75. Additionally, stress in the GaN layer raises a concern in terms of device performance. See Zhang, J. Appl. Phys., 108, 073522 (2010).
In another approach, the buffer structure is optimized to induce compressive stress in the Group IIIA-nitride layer (e.g., GaN) so that the CTE mismatch induced tensile stress can be partially compensated. An example of this technique is the use of a thin low-temperature AlN interlayer during GaN epitaxial growth. GaN grown on strain relaxed AlN or AlGaN layer is compressively stressed. As the dislocation in GaN has low mobility, the strain relaxation in GaN layer is not complete. At the end of epitaxy, a compressive stress is left in the GaN layer to compensate the tensile stress induced by CTE mismatch. See, e.g., Amano, J. Appl. Phys. 37, L1540 (1998), and Krost & Dadgar, Phys. Stat. Sol. (a) 200, No. 1, 26-35 (2003). As the AlN interlayer and the AlGaN buffer layer only partially compensate the tensile stress in GaN, the crack-free GaN thickness is still limited to a few micrometers.
In yet another approach, Group IIIA-nitrides, such as GaN, are grown on patterned substrates. See, e.g., U.S. Pat. No. 8,507,737, which discloses GaN growth on patterned sapphire substrates. See also U.S. Pub. No. 2011/004568, which discloses grooved substrates. It has also been reported that GaN may grow on patterned Si (111) substrates. See Kawaguch, phys. stat. sol. (a) 176, 553 and Sawaki, Journal of Crystal Growth 311 (2009) 2867-2874. The aim of this method is to relieve the stress at the edge of the GaN islands. However, the stress relief is only effective in GaN layers with lateral dimension of a few hundred micrometers.
Still further, GaN has been grown on compliant substrates. GaN growth on SOI substrates shows improved crystalline quality as discussed by Cao, J. Appl. Phys., 83, 3829, 1998. However, there is no detailed study on the advantage of using blanket SOI substrates in terms of crack and stress relaxation. This approach may reduce GaN defectivity but not necessarily increase the thickness of crack-free GaN.
Finally, the use of a backside CTE layer to balance wafer bow has been disclosed in U.S. Pub. No. 2012/0132921. U.S. Pub. No. 2012/0132921 discloses a method to balance the tensile stress in GaN using a CTE layer on the backside of the substrate. The challenge of this method is that the response of the CTE film to temperature change must follow that of GaN.